Free Length – The length of a probe when it has no compression on either the top or bottom or both sides of the probe

Operating Position - The specified distance from free length to the position where the top and/or bottom plunger and the compression of the internal spring and plunger to barrel connection position is optimal for a given probe design.

Travel – Defined as the Free length – Operating Position

Final Height – The length of the probe when the plungers are compressed to the stop point or maximum spring compression

Overtravel – This is a term used for probe systems that defines the amount of extra distance the prober chuck will compress the wafer probes down on the die contacts. Overtravel is set to insure full contact on all probes. In package test this could be defined as the amount of extra plunger pressure needed to make continuity on all pins.

Operating Force, Spring Force Pitch – the distance between the center of a pin to the adjacent pin. Most package devices have pitches expressed in mm and range from 0.2mm to 1.0mm for most package types.

Preload – When a socket is installed on a test PCB board, the probe plungers contacting the board pad are compressed a fixed distance defined by the design of the probe capture cavity. This is measured in both spring forge in grams or distance from full length.

Non-Magnetic – This refers to materials that do not retain a magnetic field or attract a magnetic object. These are non-ferrous metals like copper, aluminum, tin zinc, alloys such as BeCu, bronze and brass and precious metals. Stainless steel can be non-magnetic but usually is mildly to highly magnetic based on carbon or cobalt content

IMAX – Maximum DC current. The conditions for this can be defined as continuous constant current. In a spring probe this is usually defined as the amount of current over a fixed time that will be large enough to reduce the force property of the spring

Cres – Contact Resistance - The term contact resistance refers to the contribution to the total resistance of a system which can be attributed to the contacting interfaces of electrical leads and connections as opposed to the intrinsic resistance, which is an inherent property of the conducting material, independent of the measurement method. Contact resistance is one of the major issues a well-designed spring probe and socket system must overcome.

Contact resistance is based on the amount of conducting surface at the contact mating interface. Because all solid surfaces are rough on the microscale, two mating solid surfaces make contact only where the peaks of small surface asperities (roughness) touch one another.

Cres for a spring probe then is related directly to the force a spring probe can exert and the hardness of the contacting materials.

This is governed by the simple relationship

F=HxA

or Force is equal to the total area times the hardness

thus the total contact area is equal to

A=F/H

The other major impact on contact resistance is surface contamination and metal oxide layers. The spring force also has to overcome contamination to maintain the contact resistance.

Contact resistance will increase over time as the spring in the probe wears out and the surface of the probe contact deteriorates with wear.

Modulus ShearSpring Rate | Stress, stress @ OP | Force @ OP gms @OP -  Hooke's Law- states that the force needed to compress or extend a spring is directly proportional to the distance you stretch it. As an equation, Hooke's Law can be represented as F = kx, where F is the force we apply, k is the spring constant, and x is the extension of the material (typically in meters). This theory of elasticity says the extension of a spring is proportional to the load applied to it. Many materials obey this law as long as the load does not exceed the material's elastic limit.

Conic Tip Shape - Probe tip shape that comes to a single point. This type of tip is usually best for contact with a conductive plane like and LGA pad or QFN lead. This type of tip has a single small surface contact area on the pad and one force point.

Crown Tip Shape - Tip shape that comes to a multiple points. This type of tip is usually best for contact with a solder ball on a BGA or a deviice pad or lead with potential for heavy contamination or thick oxide layer. The nature of the tip creates a force to turn the probe tip slightly as it is compressed which acts as a self wiping effect which helps keep the probe tip clean.

3 point | 4 point | Ogive | Kelvin - A contact or probe that has two parallel conductors making a single contact at the pad or solder ball. This type of probe consists of two conducting paths and each tip makes contact with the test point. This allows for a force and sense connection to the pin and eliminates the loss in the contactor and test board, enabling very accurate DC measurements.

Particle Interconnect - This is a process where small chips of industrial diamond or carborundum are adhered to a contact surface and then plated with a thin coat of NiAu to form a conduction path. The particle interconnect creates many fixed surface asperities and will drive very low contact resistance since the contact area on the micro scale has been increased the hardness of the particle material.

Production Test - Production test is the process step to verify a product that is released for sale to the market meets a published standard specifications and test conditions or customer defined test condition. Production test are done using specialized automated handling equipment, usually defined at multiple temperatures (hot and cold). Production test usually means high volumes, large data collection and tight process monitoring to insure test yield is maximized.

Production test sockets main requirements include: high insertion count, long life time reliability, maintainability, first contact yield and operating margin over the AC and DC and Power transient specifications of the Device Under Test.

Device Characterization - This is the step in the development and release of a device or system that the specifications and functional operation is verified and the operating limits of the design are the device is subject to varying axis inputs and operational graphs are determined and published. Typically, high accuracy and resolution, and very wide operating margins are needed to successfully measure the limits of a device or system.

Characterization is usually an engineering activity marked by low volumes, higher cost of components and less emphasis on optimizing test efficiency and more emphasis on developing the proper test methodology. Characterization tooling will often have additional features that are added for specific tests that are then removed when moving to production where gathering detailed performance data is not required. Characterization tooling though is often designed to work on the production test equipment to allow engineering to gather correlation data on failure returns, yield issues or revision changes.

Burn-In -  This is the test process step where a part is subjected to environmental stress, usually high temperature, to accelerate the early failures that will occur. Sometime this refers to the lifetime “Bath tub Curve”. The goal is to stress the part by cycling power, running at high temperature and clocking or operating the part in a reduced mode. If there are early failure modes, these should be caught at this stage before the part is sent to a customer or added to a system. At that point failures are very expensive to repair.

Burn-In is usually performed for a long time on each part (multiples of hours or even weeks). Because of this very long test time, the test must be performed in a massively parallel test platform in an environmental chamber like an oven. In semiconductor burn-in, there can be hundreds of sockets needed for a specific part. This drives burn-in sockets and components like probes to as low a cost as possible. The probes used in burn in do not have to cycle the number of insertions a production socket requires so these probes can be made lower cost materials and a stamped manufacturing process. The sockets can be designed with simple clamping mechanisms and lower cost materials.

Impedance - Generally, Electrical impedance is the measure of the opposition that a circuit presents to a current when a voltage applied. The concept of impedance in AC circuits is necessary because there are two additional impeding mechanisms to be considered besides the normal resistance of DC circuits: first is the induction of voltages in conductors self-induced by the magnetic fields of the varying currents (inductance), and the electrostatic storage of charge induced by voltages between conductors (capacitance).

Impedance is defined as the frequency domain ratio of the voltage to the current. In other words, it is the voltage–current ratio for a single complex exponential at a particular frequency ω.

The impedance of a conductor can be roughly determined by the equationImpedance in a probe or socket is determined by how the physical dimensions of the connector, i.e the pin diameters, pitch, ground arrangement, socket material create capacitance and inductance variance at specific frequencies.

Resonant Frequency - The resonance of a probe, which is a series RLC circuit, occurs at the frequencies where the inductive and capacitive reactances are equal in magnitude but cancel each other because they are 180 degrees apart in phase. The sharp minimum in impedance which occurs at this frequency can be useful in tuning applications or It can be detrimental to the operation of a probe or test circuit by causing unwanted sustained and transient oscillations that may cause noise or signal distortion through ringing and unwanted oscillation.

S-parameters - Scattering parameters or S-parameters (the elements of a scattering matrix or S-matrix) describe the electrical behavior of linear electrical networks when undergoing various steady state stimuli by electrical signals.

In the S-parameter approach, an electrical network is regarded as a 'black box' containing various interconnected basic electrical circuit components or lumped elements such as resistors, capacitors, inductors and transistors, which interacts with other circuits through ports. The network is characterized by a square matrix of complex numbers called its S-parameter matrix, which can be used to calculate its response to signals applied to the ports.

In the case of a socket, a single pin with an input and output has 2 ports. S11 is the energy reflected from the waveform introduced at one end of the probe, S22 is the reflected energy from the opposite end of the probe. S12 is the energy transmitted from port 1 to port 2 and S21 is from port 2 to port 1. In the case of a completely symmetrical physical/mechanical probe design S12 = S21 and S11 = S22.

S12 and S21 are referred to as Insertion Loss. S11 and S22 are referred to as return loss

4 Port S-Parameters - 4 Port S Parameters are used to characterize 4 port networks. They provide information regarding the reflected and incident power waves between the 4 ports of the network.

This more closely represents the signal paths found in a test socket. 4 Port and larger) S- parameter matrices are commonly used to analyze a pair of coupled transmission lines to determine the amount of cross- talk between them, if they are driven by two separate single ended signals or separate legs of adjacent differential pairs, or the reflected and incident power of a differential signal driven across them.

Many specifications of high speed differential signals define a communication channel in terms of the 4-Port S-Parameters, for example the 10-Gigabit Attachment Unit Interface (XAUI), SATA, PCI-X, and InfiniBand systems. These types of SerDes ports are often integrated into large system level devices.

Insertion Loss -  Insertion loss is the loss of signal power resulting from the insertion of a device in a transmission line. It is usually is usually expressed in decibels (dB), expressed across a frequency range and is measured on a network analyzer. The S-parameter that refers to Insertion loss in a single ended channel is S12, S21.

In a socket or spring probe, as a passive element, the insertion loss is simply the amount of signal power that arrives at one end of the probe as compared to the signal before it enters the probe signal path. Insertion loss varies over frequency it will be plotted as a graph of loss vs frequency of the measurement signal

Return Loss - Return loss is the loss of power in the signal returned/reflected by a discontinuity in a transmission line or test connector. This discontinuity originates from a mismatch of the channel impedance to the terminating load or with a device inserted in the line. It is usually expressed as a ratio in decibels (dB).

Return loss is measured on a network analyzer and labeled as S11 or S22 in reference to the S-matrix and the port where the reflected power originates.

Return loss varies over frequency and for a passive element like a spring probe is a measure of the reflected energy from the probe due to its impedance

Bandwidth - Bandwidth is a term with many contexts. The word bandwidth applies to signals, filters computing systems, sampling theorem, but in the application of a test socket or spring probe, it refers to a communication channel modeled as a low pass filter. A channel with a certain bandwidth means that the system can process signals of that bandwidth, or that the system reduces the bandwidth of a white noise (all frequencies) input to that bandwidth.

The 3dB bandwidth of a communication channel is the part of the system's frequency response that lies within 3 dB of the response at its peak, which in the low pass filter is near 0 hertz. If the maximum gain is 0 dB, the 3 dB bandwidth is the frequency range where the gain is more than −3 dB, or the attenuation is less than 3 dB. This is also the range of frequencies where the amplitude gain is above 70.7% of the maximum amplitude gain, and the power gain is above half the maximum power gain.

The standard for determining bandwidth for a passive element like a probe is more stringent and is usually limited to the frequency where the attenuation is less than 1dB. This derives from a history of trying to make the interconnects transparent to the test and not using a probe compensation (de-embedding) or simulation approach to socket/test channel design.

I/O - For a serial or digital communications channel, the term IO refers to the transmitter and receiver pins used to communicate between system or chip level components. For a serial channel, these are usually located on separate pins on the package or in most cases a pair of pins (p/n) used for differential signaling. Modern high speed parallel memory bus pins like DDR4, usually have a single pin for input and a single pin for output, but some older memory bus technology and slower speed IO will use uses the same pin for both input and outputs which saves on pin count.

SerDes - Acronym that stands for Serializer/Deserializer. The primary use of a SerDes is to provide data transmission over a single/differential line to minimize the number of I/O pins and interconnects and maximize the data throughput of the channel. SerDes channel IO always come in pairs, A Tx (transmit block) and an Rx (receive block) though these blocks do not have to reside on the same chip, an Rx Tx pair is most likely on any reasonably integrated devices except where the specific SerDes Design Calls for directional transmission and reception of data. SerDes almost always refers to serial digital data transmission over a solid medium as opposed to RF wireless protocols

Protocols – The encoding and signal definition used for a specific SerDes design.  There are many types of protocols some listed here include:

• PCIe or PCI express (1X,2X,3X), this a popular design for serial ports to talk to peripherals especially video and GPU processors
• GigaBit Ethernet 1GB, 10 GB and 100 GB
• OIF (Optical Interfacing Forum) CEI (Common Electrical Interoperability)
• FibreChannel
• XAUI
• SPI-4
• PAM and PAM-4 (Pulse Amplitude Modulation)

Eye Diagram - An eye diagram is used in electrical engineering to get a good idea of signal quality in the digital domain. To generate a waveform analogous to an eye diagram, we can apply infinite persistence to various analog signals a well as to quasi-digital signals such as square wave and pulse as synthesized by an arbitrary frequency generator (AFG).

Here, the bit sequences 011, 001, 100, and 110 are superimposed over one another to obtain the example eye diagram.

The eye diagram takes its name from the fact that it has the appearance of a human eye. It is created simply by superimposing successive waveforms to form a composite image. The eye diagram is used primarily to look at digital signals for the purpose of recognizing the effects of distortion and finding its source

Sockets and interconnects will introduce reflections and signal loss and distortion into the SerDes channel. Socket pins are passive elements and will always add to the total channel eye closure. Key issue for a socket pin is to not reduce the eye opening enough to cause the part to fail.

Bit Rate - In telecommunications, computing and digital communications, bit rate is the number of bits (1/0) that are conveyed or processed per unit of time. The bit rate is quantified using the bits per second (symbol: "bit/s"), often in conjunction with an SI prefix such as” kilo” (1 kbit/s = 1000 bit/s), “mega” (1 Mbit/s = 1000 kbit/s), “giga” (1 Gbit/s = 1000 Mbit/s) or “tera” (1 Tbit/s = 1000 Gbit/s). The abbreviation "bps" is often used to replace the standard symbol "bit/s", so that, for example, "1 Mbps" is used to mean one million bits per second.

One byte per second (1 B/s) corresponds to 8 bit/s. This is the measure for Bit Rate over parallel channels or data throughput. Each serial protocol has a standards Bit Rate. For instance PCIex2 has 5 Gb/s bit rate but due to the ten bit encoding, a single PCIe 2 channel has data throughput of 500 MB/s.

Differential Signaling - This is a method for electrically transmitting information using two complementary signals. The technique sends the same electrical signal as a difference pair of signals, each in its own conductor. The pair of conductors can be wires or traces on a circuit board. The key advantage of differential signal is what is known as common mode noise rejection. The measurement is taken as the voltage difference between the two wires. Noise common to the signal [pairs, like cross talk, is subtracted from the signal pair at the differential receiver

Tx - The transmitter portion of a SerDes IO channel. The Tx pin is charged with sending a serial data stream to a receiver channel. Modern SerDes use differential signaling and also require a number of signal conditioning design enhancements to operate at very high bit rates in PC board mediums with high signal loss. Some types of Tx signal conditioning include pre-conditioning the signal using pre-shoot and under shoot on the specific bit streams, impedance matching the channel, voltage trimming and very low jitter clock designs.

Rx - The receiver portion of SerDes IO Channel is a differential amplifier that recovers the signal as the difference between two input voltages. Differential receivers are noise tolerant and do not have to share the same ground as the transmitter so they are not as sensitive to threshold differences.

Link Training - Link training is a process by which the transmitter and receiver on a high-speed SerDes link communicate with each other to tune their equalization settings. Link training enables automatic tuning of the finite impulse response (FIR) filter for each channel to achieve the desired bit error rate (BER). These dynamic variations in the channel's transmitter and receiver conditions are set up during a system start or as a setup procedure before operation or test is commenced.

A Socket can impact the Link Training and overall SerDes test reliability, if it introduces a large reflection, or resonance in the signal or introduces a large enough insertion loss which shifts the compensation the link training sets in the test program to a saturation point or at a marginal area that the part would not normally operate in a system setting. This is where care and design simulation with the socket as part of the total test channel can insure that these conditions do not occur or if the socket S-parameters are at issue, the socket can be tuned to work closer to the center of the IO design margins.

Bit Error Rate (BER) - The bit error rate (BER) is the number of bit errors per unit time. The bit error ratio (also BER) is the number of bit errors divided by the total number of transferred bits during a studied time interval. Bit error ratio is a unit less performance measure, often expressed as a percentage. Bit Error Rates are expressed in very small values such as 10-12 or smaller to insure links operate with a very high probability of transmitting correct data,

Sockets, as passive elements, introduce no random jitter. However, sockets can have a component of cross talk that can contribute to what appear to be low probability link errors. Fixed distortion in the socket is usually a small component of the overall deterministic errors in the system. For a precise test result, channel effects such as the socket loss should be calibrated out of the BER measurements.

Jitter - The slight movement of a transmission signal in time or phase that can introduce errors and loss of synchronization. Jitter in a channel consists of deterministic and random jitter. Deterministic Jitter can be quantified at higher bit error rates and consist of errors caused by the band limit of the channel and the Bit Rate of the signal. Since a probe is part of the channel that contributes to the band limit, it can be a source of additional deterministic jitter. As a passive element, it will contribute to symbol to symbol interference (ISI), and when placed in a socket configuration contribute to the crosstalk component of the deterministic jitter. In the power distribution network, the probe can contribute to periodic jitter a clock circuit will need to reject, through the additional inductance it adds to the source and return paths.

A probe will not contribute to the Random Jitter. Only active elements in the system can produce random jitter power

RF Test -  RF is short for radio frequency. RF is any frequency within the electromagnetic spectrum associated with radio wave propagation. When an RF current is supplied to an antenna, an electromagnetic field is created that then is able to propagate through space. Wireless technologies are based on RF field propagation. These frequencies make up part of the electromagnetic radiation spectrum.

Electromagnetic radiation consists of waves of electric and magnetic energy moving together (that is, radiating) through space at the speed of light. Taken together, all forms of electromagnetic energy are referred to as the electromagnetic spectrum. Radio waves and microwaves emitted by transmitting antennas are one form of electromagnetic energy.

RF waves can be characterized by a wavelength and a frequency. The wavelength is the distance covered by one complete cycle of the electromagnetic wave, while the frequency is the number of electromagnetic waves passing a given point per unit of time. The frequency of an RF signal is usually expressed in terms of a unit called the hertz (Hz). One Hz equals one cycle per second. One megahertz (MHz) equals one million cycles per second. Different forms of electromagnetic energy are categorized by their wavelengths and frequencies. The RF part of the electromagnetic spectrum is generally defined as that part of the spectrum where electromagnetic waves have frequencies in the range of about 3 kilohertz (3 kHz) to 300 gigahertz (300 GHz).

Smith Chart - A Smith Chart is a graphical aid designed for electrical and electronics engineers specializing in radio frequency (RF) engineering to assist in solving problems with transmission lines and matching circuits.

The Smith chart is a plot of complex reflection overlaid with an impedance and/or admittance grid referenced to a 1-ohm characteristic impedance

The Smith chart contains almost all possible impedances, real or imaginary, within one circle. All imaginary impedances from - infinity to + infinity is represented, but only positive real impedances appear on the "classic" Smith chart. This is a complicated topic needing more background in analog RF

VSWR - VSWR (Voltage Standing Wave Ratio), is a measure of how efficiently radio- frequency power is transmitted from a power source, through a transmission line, into a load (for example, from a power amplifier through a transmission line, to an antenna)

In an ideal system, 100% of the energy is transmitted. This requires an exact match between the source impedance, the characteristic impedance of the transmission line and all its connectors, and the load's impedance. The signal's AC voltage will be the same from end to end since it runs through without interference.

In real systems such as an RF socket, mismatched impedances from the transmission channel cause some of the power to be reflected back toward the source (like an echo). Reflections cause destructive interference, leading to peaks and valleys in the voltage at various times and distances along the line.

VSWR measures these voltage variances. It is the ratio of the highest voltage anywhere along the transmission line to the lowest. Since the voltage doesn't vary in an ideal system, its VSWR is 1.0 (or, as commonly expressed, 1:1). When reflections occur, the voltages vary and VSWR is higher -- 1.2 (or 1.2:1), for instance.

Mathematically:

• VSWR is the voltage ratio of the signal on the transmission line:
• VSWR = |V(max)| / |V(min)|
• where V(max) is the maximum voltage of the signal along the line, and V(min) is the minimum voltage along the line.
• It can also be derived from the impedances:
• VSWR = (1+Γ)/(1-Γ)
• where Γ (gamma) is the voltage reflection coefficient near the load, derived from the load impedance (ZL) and the source impedance (Zo):
• Γ= (ZL-Zo)/(ZL+Zo)
• If the load and transmission line are matched, Γ = 0, and VSWR = 1.0 (or 1:1).

CAD Software - Computer-aided design (CAD) is the use of computer software to aid in the creation, modification, analysis, or optimization of design. In the case of a spring probe, CAD software can be used to create a full suite of design and operational models. These include:

• Two-dimensional mechanical drawing of the probe and sub-assemblies
• Three-Dimensional mechanical rendering of the probe and mechanical and operational view of the socket and lid assemblies, heat sinks and board to socket attachment hardware
• Finite Element Analysis of the probe operation and socket movements
• Thermal model of the socket and heat transfer for the spring probe
• SPICE model of the probe
• 3D Electromagnetic Simulation of the probe and socket design.

A probe and socket that is fully modeled and well understood eliminates most of the guess work surrounding the test interface performance and can enhance first pass yield as well as power distribution and IO performance. For the socket manufacturer, it allows for design experimentation and performance testing the expense of prototyping

3D Field Solver - This is a CAD program or extension which can calculate the electromagnetic fields within a three-dimensional structure. The structure is built in the program, dimensions input correctly, the materials of the test structure and surrounding environment are input. From the field calculations, the S-parameters time domain response and filed lines can be displayed.

Finite Element Analysis - FEA (Finite Element Analysis is a computerized method for predicting how a product reacts to real-world forces, vibration, heat, fluid flow, and other physical effects. Finite Element Analysis shows whether a product will break, wear out, or work the way it was designed.

Sockets and Probes benefit from FEA work to understand the motion and compliance of a socket as a part is inserted, thermal transfer and maximum stress points.

SPICE - (Simulation Program with Integrated Circuit Emphasis) is a general-purpose, open source analog electronic circuit simulator. It is a program used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior. It can also be used to effectively model the performance of an IC output pin model with the passive elements of the transmission channel to gauge the performance of the IO pin under the connector environment.

Spice models of sockets and spring probes consist of passive elements; Resistance (R), Inductance(L), capacitance (C) and conductance (G) as well as the mutual elements derived from the adjacent pins in a socket.

SPICE models of contacts help the engineer understand the operation of the device IO when in contact with analog lumped element equivalents of the socket and probe.

A SPICE lumped element network model of a spring probe as a single conductor (Ground, Signal, Ground) configuration. The component values are determined by measurement or 3D field solver simulation

A SPICE lumped element network model of a spring probe as a parallel conductor (Ground, Signal, Signal, Ground). This model contains mutual elements due to the coupling of the two conductors.

SPICE models of lumped elements suffer accuracy issues as the frequencies increase. The SPICE model is a linear network and as the frequency increases the probe starts to look like a transmission line.

Simulation Configuration - When describing a socket for simulation or measurement, it is usual to express the pin configuration in three areas and two patterns. The three configuration areas are:

• Edge : Pins located on the edge of a grid array or part of a QFP or similar type device with a single row of pins on each side of the device.
• Corner: Pins that reside on the corner of a grid or QFP type package
• Array: Pins that reside inside an array and surrounded on all sides by other pins

There are two type of Basic pin patterns to describe a socket measurement or simulation for edge or array configurations:

GSG: Ground Signal Ground. -  This is the configuration used to describe a single pin conductor with adjacent ground return paths in the socket.

GSSG: (Ground, Signal, Signal, Ground) This is the configuration used for parallel conductors with a ground pin on each side. This is the configuration used for differential signals.

Layer - A PCB board is made up of multiple sheets of core material laminated together in a stack. A layer can contain power planes, ground planes signal etches and VIAs or any combination of structures that can be design in 2 dimensions. A layer usually refers to the metal layers that reside in the stack up.

Stack Up - This term refers to the placement of multiple layers in a single board. A PCB board can have many layers of core material laminated together with a material called pre-preg.

Core Material - A sheet of material with 3 layers; a metal layer (copper) on top, a dielectric material and another metal (copper layer on the bottom. The height of these layers are fixed to create a spacing that allows the PCB board vendor to choose the height dimension from the bottom to the top layer that provides the correct impedance for the signal traces in the design.

Dielectric Material - An insulating material with a very high resistance to electric current can be a dielectric. When dielectrics are placed in an electric field, practically no current flows in them because, unlike metals, they have no loosely bound, or free, electrons that may drift through the material. Instead, electric polarization occurs.

Because of dielectric polarization, positive charges are displaced toward the field and negative charges shift in the opposite direction. This creates an internal electric field that reduces the overall field within the dielectric itself. If a dielectric is composed of weakly bonded molecules, those molecules not only become polarized, but also reorient so that their symmetry axes align to the field.

Dielectric typically means materials with a high polarizability as opposed to an insulator which refers to low electrical conduction. Dielectrics are expressed by a number called the relative permittivity (also known as the dielectric constant). The term insulator is generally used to indicate electrical obstruction while the term dielectric is used to indicate the energy storing capacity of the material (by means of polarization). A common example of a dielectric is the electrically insulating material between the metallic plates of a capacitor. The polarization of the dielectric by the applied electric field increases the capacitor's surface charge for the given electric field strength.

Trace and Signal Etches - In a printed circuit board, the signal traces or etches, including voids and signal pads, are placed onto the copper layers with a photo-etch process. Hence the printed nature of the PCB. Structurally there are two types of PCB trace designs that are used. These are Micro-strip and Strip Line.

These signal traces connect pins on the various circuit pins on the board. Layout is done using one of several CAD software PCB layout tools that aids the designer in positioning the traces, routing the signals correctly and guiding the design through the processes of creating the PCB board.

Micro-strip - On a PCB, traces etched on an outside layer are called micro-strip. Since only one side of the trace is in contact with the core dielectric, the physical dimensions of the etch are different than a trace embedded in the board for a given trace impedance. This is due to the air on one side and the faster propagation time the EM field experiences in air versus the core dielectric.

The cross section of a micro-strip trace has A: the conductor; B:Air; C: Dielectric and; D: the ground plane.

Micro-strip is usually the choice for signals that need to propagate faster or run at higher frequencies since the air side of the transmission line is an almost ideal dielectric. Simple 2-4 layer boards use micro-strip traces to route the signals as well

Strip Line -  A strip line printed circuit etch uses a flat strip of metal which is sandwiched between two parallel ground planes. The insulating material of the surrounding substrate forms a dielectric. The width of the strip, the thickness of the substrate and the relative permittivity or dielectric constant of the substrate determine the characteristic impedance of the strip which is a now a controlled transmission line. As shown in the diagram, the central conductor need not be equally spaced between the ground planes. In the general case, the dielectric material may be different above and below the central conductor.

To prevent the propagation of unwanted modes, the two ground planes must be shorted together.

B is the top layer ground, A is the transmission line etch, C is the dielectric substrate and D is the bottom layer ground.

In a printed circuit board stack up, a strip line circuit requires 2 pieces of core material and a laminating layer called a pre-preg.

The top layer GND the substrate and the signal etch come from one core, prepreg is added to laminate the next layer and a second core sheet placed below and the layers can be etched on the second layer and connected with VIAs.

Pre-preg - A pre-preg (from pre-impregnated) is fiberglass or similar dielectric material impregnated with resin. The resin is pre-dried, but not hardened, so that when it is heated, it flows, sticks, and is completely immerses around the planes, traces and pads that are printed on a layer. Prepregs are thus fiberglass strengthened by an adhesive layer used to laminate core materials to build a PCB stack up.

Coplanar Waveguide -  A PCB Coplanar Waveguide is another type of micro-strip trace etch. A coplanar waveguide must be placed on an outside layer in the PCB stack as a surface etch. It is an electrical planar transmission line, and is typically used to convey microwave-frequency signals. On a smaller scale, coplanar waveguide transmission lines are also built into monolithic microwave integrated circuits.

A coplanar waveguide (CPW) consists of a single conducting track printed onto a dielectric substrate, together with a pair of return conductors, one to either side of the signal trace.

All three conductors are on the same side of the substrate, and hence are coplanar. The return conductors are separated from the central track by a small gap, which has an unvarying width along the length of the line. Away from the central conductor, the return conductors usually extend to an indefinite but large distance, so that each is notionally a semi-infinite plane.

VIA -  A via or VIA on a PCB or IC is an acronym for Vertical Interconnect Access. A VIA is an electrical connection between layers in a physical circuit that goes through the plane of one or more adjacent layers.

In a printed circuit board design, a via consists of two pads in corresponding positions on different layers of the board, that are electrically connected by a hole through the board. The hole is made conductive by electroplating. High- density multi-layer PCBs may have microvias which are defined as: blind vias which are exposed only on one side of the board; buried vias connect internal layers without being exposed on either surface. Thermal vias carry heat away from power devices and are typically used in arrays.

A via consists of:

• Barrel — conductive tube filling the drilled hole
• Pad — connects each end of the barrel to the component, plane or trace
• Antipad — clearance hole between barrel and metal layer to which it is not connected

A IC test socket acts very much like a via to the Device Under Test from the board that interfaces with the automatic test platform. A socket will carry Power GND and signals directly to the DUT from the device socket pads that have been laid out on the DUT boards